Power MOS devices, including lateral diffused MOS (LDMOS) devices, are generally difficult to manufacture in SOI, although the benefits of using an SOI process to enhance the high-frequency performance of discrete or integrated LDMOS devices, particularly in a radio frequency (RF) range of operation (e.g., above one gigahertz), are known.
In an article by J. Cai et al., “A Partial SOI Technology for Single-Chip RF Power Amplifiers,” IEEE IEDM, pp. 40.3.1-40.3.4, 2001, a process is described for building an RF LDMOS device in partial SOI by employing multiple trench and dielectric etching to form thin “walls” of silicon, and then oxidizing these walls to form one layer of SOI under the drain region of the RF LDMOS device and away from the channel region. This methodology, however, undesirably forces a significant portion of the lightly-doped drain (LDD) region of the device to be in contact with the p-type substrate, and thus does not allow the on-resistance of the device to be reduced by increasing the doping of the LDD region. Furthermore, fabricating the RF LDMOS device using the partial SOI process is difficult to manufacture and is therefore costly.
In another article, authored by S. Matsumoto et al., “A Quasi-SOI Power MOSFET for Radio Frequency Applications Formed by Reversed Silicon Wafer Direct Bonding, IEEE Transactions on Electron Devices, Vol. 48, No. 7, pp. 1448-1453, July 2001, a process is described in which after an LDMOS device is fabricated but before metalization, a thick oxide layer is deposited on the device wafer and a second wafer is bonded to the device wafer. The device wafer is then inverted and thinned substantially so that only the top region remains. More processing is then done to build the dielectric oxide on top of the active portion of the device, and then metalization is added. The source, drain and gate terminals are brought out only from an upper surface of the device wafer. In an RF LDMOS device formed using this process, the doping in the LDD region significantly affects the breakdown voltage, and thus the doping concentration of the LDD region cannot generally be increased without also reducing the breakdown voltage. Therefore, like in the previously described methodology, the on-resistance generally cannot be reduced in an LDMOS device formed using this process. Moreover, the fabrication process is difficult and costly to implement.
There exists a need, therefore, for techniques for forming an MOS device capable of improved performance and reliability that does not suffer from one or more of the above-noted deficiencies associated with conventional MOS devices.